The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multi-thread processor that executes multiple threads at the same time.
In recent years, in order to improve the processing capacity of a processor, a multi-thread processor has been proposed. The multi-thread processor has threads each issuing an independent instruction flow. The multi-thread processor executes arithmetic processing while switching by which thread the instruction flow issued should be processed by an arithmetic circuit that processes an instruction by pipeline processing. In this situation, the multi-thread processor can process an instruction issued by another thread in another execution stage while executing an instruction issued by one thread in one execution stage in a pipeline. That is, in the arithmetic circuit of the multi-thread processor, the instructions independent of each other are executed in the respective different stages. As a result, the multi-thread processor reduces a time during which no instruction is processed in the execution stage in the pipeline while smoothly processing the respective instruction flows, and improves the processing capacity of the processor.
Also, the multi-thread processor of this type conducts the processing of temporarily enhancing the processing capacity on a given thread by stopping a part of the plural threads to be executed In this way, the technique of dynamically switching the number of threads to be executed is disclosed in Japanese Unexamined Patent Application Publication No. 2004-326749.
Also, there is a virtualization technique of making a single physical resource (hardware resource) look like multiple resources. With the use of this virtualization technique, for example, multiple virtual machines (VM: virtual machine) can be operated on one CPU as a result of which different operating systems (OS: operating systems) can be operated on the respective virtual machines. The multiple virtual machines which are operated, can be represented by a physical CPU or memory, being virtualized to generate a logical partition by another expression. In the present specification, the expression “partition” is used as the same meaning as that of the virtual machine.
Japanese Unexamined Patent Application Publication No. 2004-326749 discloses a device for controlling the multi-thread processor in a computer that is logically partitioned. The logically partitioned computer includes multiple partitions, and a partition manager that controls the multiple partitions. Also, in the multi-thread processor disclosed in Japanese Unexamined Patent Application Publication No. 2004-326749, a first hardware thread among multiple hardware threads is assigned to a logical processor which is present in a first partition among the multiple partitions. Further, the device disclosed in Japanese Unexamined Patent Application Publication No. 2004-326749 includes a control circuit which is configured to selectively activate and inactivate the first hardware thread among the multiple hardware which is executed by the multi-thread processor, and also configured to control a method of activating the first hardware thread once the first hardware thread is inactivated. The partition manager of the device disclosed in Japanese Unexamined Patent Application Publication No. 2004-326749 instructs the control circuit to regard a logical processor as off-line in the first partition, to thereby prohibit the reactivation of the first hardware thread responsive to an expression of interrupt, and inactivate the hardware thread.
With the above configuration, the device disclosed in Japanese Unexamined Patent Application Publication No. 2004-326749 inactivate the first hardware thread among the multiple hardware threads, and improves the processing capacity of other hardware threads.